진학프로석·박사 채용 접수 플랫폼

Current research in neural network efficiency include heterogeneous quantization, custom number representation, sparse data storage, etc. In order to demonstrate efficiency improvements of hardware implementation of neural networks, fully operational FPGA prototyping is necessary to
exhibit convincing results. This is a challenge that requires a significantly high development effort. We have research-purpose experiment tools able to model and generate quantized neural networks for FPGA acceleration experiments.

This framework is composed of a software tool (C/C++) and a set of hardware components developped at RTL level for hardware implementation of layers of networks. It supports a certain number of functionalities to create custom and optimized implementations, such as per-layer arbitrary quantizations, pipeline throughput balancing, some forms of operator customization, parameter compression, etc.

The software tool is in charge of the following tasks:

- modelling the networks and theyr layers with all necessary low-level hardware implementation details

- generating the necessary RTL files and configuration that implements the corresponding hardware pipelines

- and configuring and controlling the hardware accelerator to execute accelerated inference tasks.

The hardware components include usual network layers, notably convolutions, pooling, activation, fork and concat for execution in parallel of series of layers, etc.

Additional development and maturation are necessary in order to release a version that is solid enough for public and industrial experiments.

The capabilities of the framework will be extended in order to demonstrate functionality and real-time performance on complex and/or large networks. Depending on expertise, the candidate will help the team on the following tasks and research directions :

- improve integration of the framework with learning/inference
framework (PyTorch, Keras, AIDGE, ...)

- improve implementations of low-level layer implementations

- extend hardware developments to use near-FPGA DDR and HBM memories

- create functional demos using networks of interest (Yolo, Resnets, LLMs, ...)

- create proof-of-concept implementations for compression, heterogeneous quantization, etc

- reproduce state of the art network parameters with extreme quantization and compression of parameters

- design and implement next-generation hardware-friendly inference solutions

- participate to publication and valorization of these works