진학프로석·박사 채용 접수 플랫폼

Presentation of the CROMA laboratory

Supervisory bodies: Université Grenoble Alpes, Grenoble INP, Université Savoie Mont-Blanc, CNRS
Created in 2007, the laboratory is part of a long tradition of the site concerning the study of components, integrated devices and systems, whether electronic, electromagnetic or photonic. This work is carried out in constant interaction with the socio-economic and scientific environment of the two sites (Grenoble and Bourget- du-lac). CROMA's research activities cover a very wide spectrum ranging from CMOS microelectronics (CMNE team) to photonics (PHOTO team) via millimeter waves and terahertz (DHREAMS team). They concern research in micro and nano-technologies (characterization, simulation, modeling), as well as in the design and characterization of circuits, microsystems and systems.
Located at the convergence of many sciences and technologies involving electronics in the broad sense of the term, CROMA wants to play a unifying role both at regional (FMNT, MINALOGIC) and European (SiNANO Institute) levels to carry out ambitious projects concerning the information sciences and technologies of the future in the fields of the environment (photovoltaics and sensors for the nuclear industry). health (interaction between waves
and living organisms, microsystems for injecting drugs) or transport (Lidar for aeronautics and trains).

Context and motivation

As a result of the reduction in the size of CMOS transistors, low-frequency noise (LFN) due to charge trapping/detrapping in the gate dielectric is becoming increasingly important, as its amplitude is inversely proportional to the surface area of the gate oxide. This also leads to a sharp increase in dynamic variability, whichincreasingly disrupts the operation of electrical circuits and reduces the design margin of the circuits (Fig. 1). This is particularly the case for the reading circuits of CMOS imager applications; especially for low illumination where noise limits the sensitivity of the sensor.
For small transistors, this noise variability is also a result of a specific noise type called "Random Telegraph Noise" (RTN), which has specific temporal and frequency properties (Fig. 2). Specifically, this type of noise consists of sudden, high-amplitude transitions of the current passing through the transistor observed in the time domain. On the one hand, this effect endangers the stability of the digital circuits, and on the other hand, it leads to the co-existence of several DC operating points, due to the fact that its amplitude can reach 10-20% of the DC value.
Despite numerous studies on the physics of RTN, there are still many unanswered questions. The type of defects, their location in gate oxide but potentially also in STI or silicon channel, as well as their electrical signatures and underlying physical models are still subject to discussion. In addition, the extraction of the parameters characterizing RTN can also be complicated, especially when several traps are active at the same time. This requires the development of robust and accurate extraction methods that can process a large number of measurements. Concerning the measurement part, although there have been many publications with many experimental results, no systematic study of RTN for FDSOI and more specifically as a function of temperature (and specific process parameters such as channel doping or gate stack) has been done.
An initial work has already been performed, and some of the results were published in [24]. The study highlights
the influence of the trap's lateral position on the corresponding RTN amplitude in both weak and strong inversion
modes, with a contribution from both carrier number and mobility fluctuations, in conjunction with short-channel
effects. However, there is still a need for further simulations and development of explicit modeling expressions,
as well as accurate parameter extraction from the measured experimental results.

Methodology

The post-doc researcher will be responsible for a set of TCAD simulations with the Synopsys SENTAURUS tool on a
simple (reference) FD-SOI MOSFET structure to obtain:
1) the electrostatic impact of a trap on the total charge, according to its position along the channel, its depth in the oxide, the dimensions of the channel and the different operating regimes of the MOSFET, as well as the temperature
2) the charge density and the local potential in the vicinity of the trap, necessary for the theoretical calculation (with SRH or NMP models) of τc and τe.
In interaction with the simulations, the post-doc will perform experimental characterization of Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) in FD-SOI components of ST Microelectronics, including critical extractions of parameters such as oxide trap density and the characteristics of each detected RTN pulse. A strong focus will be given to the dependence with temperature, and by using CROMA's cryo stations we will be
able to achieve even 4K if necessary. In addition, measurements at ST Crolles will probably be possible.