진학프로석·박사 채용 접수 플랫폼

Context: With the continued advancement in assembly and packaging technologies such as innovative FOWLP platforms/concepts, brought by high demand for more functionality, increased I/O count, smaller/thinner form and cost reduction, temporary bonding & debonding technology (TBD) has been further developed to address new process challenges. In this regard, temporary carrier technology transcends its traditional function of providing thinned wafer handling solutions: it becomes a key element in enabling functional diversification through heterogenous integration in the FOWLP concept. The core of the temporary carrier support system is the selection of TBD materials and the carrier. Typically, a dedicated release tapes are used to fix the dies onto a temporary carrier during molding & redistribution line (RDL) processes. Challenges include coating uniformity, appropriate mechanical properties (Tg, CTE, thermal stability) and chemical resistance. These materials must also demonstrate good adhesion to the epoxy mold compound (EMC) and RDL dielectric layer yet successfully debond without damaging the FOWLP package. Thus, we propose this project to develop temporary bonding/debonding process required for FOWLP flow’s steps.

Topic: We are looking for a well-qualified and highly motivated student to develop new TBD processes for FOWLP to integrate heterogeneous active chips (HBM, ASIC) and passive interconnect/thermal chips using a molding approach. The successful candidate will oversee (i) conducting a literature review of methods and materials used for TBD process to understand their properties and associated challenges, (ii) selecting 2-3 candidates of commercially available release tape,(iii) developing the complete temporary bonding and debonding process route,(iv) perform complete morphological & mechanical characterizations of the temporary release carrier to determine the quality and performance of the TBD process. Integrity validations of TBD process after the interconnection of molded chips will be targeted, considering EMC surface roughness, planarization and carrier warpage requirements. These evaluations will be performed in close collaboration with IBM engineers.

Work Supervision: This Postdoc project will be realized under the co-direction of Pr. Dominique Drouin and Pr. Serge Ecoffey, as part of the IBM/NSERC Alliance Project on Multi-Chip Heterogeneous Integration for High Performance Computing. The work will be done mainly at the Interdisciplinary Institute for Technological Innovation (3IT) at the Université de Sherbrooke and at the MiQro Innovation Collaborative Center (C2MI) in Bromont. 3IT is a unique institute in Canada, specializing in the research and development of innovative technologies for energy, electronics, robotics and health. C2MI is an international center for collaboration and innovation in the MEMS and encapsulation field. It is the essential link between applied research and the marketing of microelectronics products. The student will thus benefit from an exceptional research environment that combines students, professionals, professors and industrialists working hand-in-hand to develop the technologies of the future.